module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    reg	[1:0]	ss_ena;
    reg	[1:0]	mm_ena;
    reg	[1:0]	hh_ena;

    assign ss_ena[0] = ena;
    
    //秒个位计时
    always @(posedge clk) begin
        if(reset) begin
            ss[3:0] <= 4'd0;
            //ss_ena[1] <= 1'b0;
        end
        else if(ss_ena[0]) begin
            if(ss[3:0] == 4'd9) begin
                ss[3:0] <= 4'd0;
                //ss_ena[1] <= 1'b1;
            end
            else begin
                ss[3:0] <= ss[3:0] + 1'b1;
                //ss_ena[1] <= 1'b0;
            end
        end
    end
    //秒十位计时
    assign ss_ena[1] = ((ss[3:0] == 4'd9) && ss_ena[0]);
    always @(posedge clk) begin
        if(reset) begin
            ss[7:4] <= 4'd0;
            //mm_ena[0] <= 1'b0;
        end
        else begin
            if((ss[7:4] == 4'd5) && ss_ena[1]) begin
                ss[7:4] <= 4'd0;
                //mm_ena[0] <= 1'b1;
            end
            else begin
                ss[7:4] <= ss[7:4] + ss_ena[1];
                //mm_ena[0] <= 1'b0;
            end
        end
    end
    
	//分个位计时
    assign mm_ena[0] = (ss[7:4] == 4'd5) && ss_ena[1];
    always @(posedge clk) begin
        if(reset) begin
            mm[3:0] <= 4'd0;
            //mm_ena[1] <= 1'b0;
        end
        else begin
            if((mm[3:0] == 4'd9) && mm_ena[0]) begin
                mm[3:0] <= 4'd0;
                //mm_ena[1] <= 1'b1;
            end
            else begin
                mm[3:0] <= mm[3:0] + mm_ena[0];
                //mm_ena[1] <= 1'b0;
            end
        end
    end
    //分十位计时
   	assign mm_ena[1] = (mm[3:0] == 4'd9) && mm_ena[0];
    always @(posedge clk) begin
        if(reset) begin
            mm[7:4] <= 4'd0;
            //hh_ena[0] <= 1'b0;
        end
        else begin
            if((mm[7:4] == 4'd5) && mm_ena[1]) begin
                mm[7:4] <= 4'd0;
                //hh_ena[0] <= 1'b1;
            end
            else begin
                mm[7:4] <= mm[7:4] + mm_ena[1];
                //hh_ena[0] <= 1'b0;
            end
        end
    end
  
    //时个位计时
    assign hh_ena[0] = (mm[7:4] == 4'd5) && mm_ena[1];
    always @(posedge clk) begin
        if(reset) begin
            hh[3:0] <= 4'd2;
            //hh_ena[1] <= 1'b0;
        end
        else begin
            if((hh[3:0] == 4'd9) && hh_ena[0]) begin
                hh[3:0] <= 4'd0;
                //hh_ena[1] <= 1'b1;
            end
            else if((hh[7:0] == 8'h12) && hh_ena[0]) begin
                hh[3:0] <= 4'd1;
                //hh_ena[1] <= 1'b0;
            end
            else begin
                hh[3:0] <= hh[3:0] + hh_ena[0];
                //hh_ena[1] <= 1'b0;
            end
        end
    end
    //时十位计时
    assign hh_ena[1] = (hh[3:0] == 4'd9) && hh_ena[0];
    always @(posedge clk) begin
        if(reset) begin
            hh[7:4] <= 4'd1;
            //pm <= 1'b0;
        end
        else begin
            if((hh[7:0] == 8'h12) && hh_ena[0]) begin
                hh[7:4] <= 4'd0;
                //pm <= ~pm;
            end
            else begin
                hh[7:4] <= hh[7:4] + hh_ena[1];
            end
        end
    end
    
    always @(posedge clk) begin
        if(reset) begin
           	pm <= 1'b0; 
        end
        else begin
            if((hh[7:0] == 8'h11) && hh_ena[0]) begin
               	pm <= ~pm; 
            end
            else begin
               	pm <= pm; 
            end
        end
    end
    
endmodule
